Some memory systems produce variable latencies, or delays, in the time required for the memory system to make data available to or to receive data from an external device in response to a read or write command. An example of such a memory system is a pseudo-static random access memory (PSRAM) device, which utilizes a self-refresh scheme to maintain the proper status of data stored therein.
In a PSRAM system, if a read or write command is received while a self-refresh operation is in progress, the refresh operation must be completed before the system can perform its data output or data input functions. As a result, the time required for the PSRAM to receive data from the external device in response to a write command, for instance, will vary depending on whether the write command was received while a refresh operation was in progress. Delays incurred as a result of waiting for on-going refresh operations to be completed increase the PSRAM's response time and thus, decrease system bandwidth.
Additionally, because of this variable latency, PSRAM systems must employ a so-called “wait” signal to indicate to an external device accessing the memory system when valid data is present on a memory system data bus (DQ bus) during a read operation and when the memory system is ready to accept data during a write operation. The external device samples the status of the wait signal to synchronize data transfers with the PSRAM. Unfortunately, at high system clock frequencies, this sampling and synchronization process can consume multiple clock cycles, thereby decreasing system performance. Furthermore, if the external device is unable to sample the wait signal within a time allowed by PSRAM operating characteristics, synchronization may fail to be achieved between the external device and the PSRAM, resulting in data errors.